annotate operator_def/assemble_D1.m @ 826:b94bb6ffa38b feature/operator_files

rename d2_2 to D1_standard_2
author Ylva Rydin <ylva.rydin@telia.com>
date Mon, 10 Sep 2018 17:48:48 +0200
parents ed8d34894589
children f82da6644f42
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
821
95c26000c0ba Add files for parsing operator data stencil file
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
1 function [D1,e_l,e_r] = assemble_D1(stencil,h,m)
826
b94bb6ffa38b rename d2_2 to D1_standard_2
Ylva Rydin <ylva.rydin@telia.com>
parents: 824
diff changeset
2 stencil_variables = read_stencil(stencil);
823
5c8b1a3bd0e6 rename boundart_stencil and and boundary_block to boundary_stencils
Ylva Rydin <ylva.rydin@telia.com>
parents: 822
diff changeset
3 D1 = assemble_op(stencil_variables.inner_stencil,stencil_variables.boundary_stencils,m)/h;
824
ed8d34894589 fix bug in assemble_D1
Ylva Rydin <ylva.rydin@telia.com>
parents: 823
diff changeset
4 [e_l, e_r] = assemble_boundary_op(stencil_variables.e,m);
821
95c26000c0ba Add files for parsing operator data stencil file
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
5 end