changeset 826:b94bb6ffa38b feature/operator_files

rename d2_2 to D1_standard_2
author Ylva Rydin <ylva.rydin@telia.com>
date Mon, 10 Sep 2018 17:48:48 +0200
parents 32c360bb480e
children d1e5143d67ed
files operator_def/D1_standard_2 operator_def/assemble_D1.m operator_def/assemble_opTest.m operator_def/d2_2
diffstat 4 files changed, 12 insertions(+), 13 deletions(-) [+]
line wrap: on
line diff
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/operator_def/D1_standard_2	Mon Sep 10 17:48:48 2018 +0200
@@ -0,0 +1,10 @@
+# D1 order 2
+
+boundary_stencils
+-1 1 
+
+inner_stencil
+-1/2 0 1/2 
+
+e
+1 0
\ No newline at end of file
--- a/operator_def/assemble_D1.m	Mon Sep 10 17:42:30 2018 +0200
+++ b/operator_def/assemble_D1.m	Mon Sep 10 17:48:48 2018 +0200
@@ -1,6 +1,5 @@
 function [D1,e_l,e_r] = assemble_D1(stencil,h,m)
-  stencil_variables = read_stencil(stencil);
-  
+  stencil_variables = read_stencil(stencil);  
   D1 = assemble_op(stencil_variables.inner_stencil,stencil_variables.boundary_stencils,m)/h;
   [e_l, e_r] = assemble_boundary_op(stencil_variables.e,m);
   end
\ No newline at end of file
--- a/operator_def/assemble_opTest.m	Mon Sep 10 17:42:30 2018 +0200
+++ b/operator_def/assemble_opTest.m	Mon Sep 10 17:48:48 2018 +0200
@@ -21,7 +21,7 @@
 op = sbp.D2Standard(m,{0 3},2);
 h = op.h;
 
-[D1,e_l,e_r] = assemble_D1('d2_2',h,m);
+[D1,e_l,e_r] = assemble_D1('D1_standard_2',h,m);
 
 verifyEqual(testCase,D1,op.D1,'AbsTol',1e-10)
 verifyEqual(testCase,e_l,op.e_l,'AbsTol',1e-10)
--- a/operator_def/d2_2	Mon Sep 10 17:42:30 2018 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,10 +0,0 @@
-# D1 order 2
-
-boundary_stencils
--1 1 
-
-inner_stencil
--1/2 0 1/2 
-
-e
-1 0
\ No newline at end of file