Mercurial > repos > public > sbplib
annotate operator_def/assemble_opTest.m @ 828:f82da6644f42 feature/operator_files
Fixed bug in tests
author | Ylva Rydin <ylva.rydin@telia.com> |
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date | Mon, 10 Sep 2018 19:17:41 +0200 |
parents | d1e5143d67ed |
children | e15a667ffde2 |
rev | line source |
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821
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Add files for parsing operator data stencil file
Ylva Rydin <ylva.rydin@telia.com>
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1 |
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2 function tests = assemble_opTest() |
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3 tests = functiontests(localfunctions); |
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4 end |
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5 |
825 | 6 function TestAssemble_op(testCase) |
821
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7 m = 10; |
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8 op = sbp.D2Standard(m,{0 1},4); |
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9 h = op.h; |
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10 |
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11 boundary_block = op.D1(1:4,1:6)*h; |
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12 inner = op.D1(5,3:7)*h; |
828 | 13 D1_new = assemble_op(inner,boundary_block,m,-1)/h; |
821
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14 |
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15 verifyEqual(testCase,D1_new,op.D1,'AbsTol',1e-10) |
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16 |
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17 end |
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18 |
825 | 19 function TestAssembleD1(testCase) |
20 m = 10; | |
21 op = sbp.D2Standard(m,{0 3},2); | |
22 h = op.h; | |
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23 |
826
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rename d2_2 to D1_standard_2
Ylva Rydin <ylva.rydin@telia.com>
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24 [D1,e_l,e_r] = assemble_D1('D1_standard_2',h,m); |
821
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25 |
825 | 26 verifyEqual(testCase,D1,op.D1,'AbsTol',1e-10) |
27 verifyEqual(testCase,e_l,op.e_l,'AbsTol',1e-10) | |
28 verifyEqual(testCase,e_r,op.e_r,'AbsTol',1e-10) | |
29 end | |
827
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parents:
826
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30 |
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parents:
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31 |
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parents:
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32 function TestAssembleD2(testCase) |
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Ylva Rydin <ylva.rydin@telia.com>
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33 m = 10; |
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Ylva Rydin <ylva.rydin@telia.com>
parents:
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34 op = sbp.D2Standard(m,{0 3},2); |
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Ylva Rydin <ylva.rydin@telia.com>
parents:
826
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35 h = op.h; |
d1e5143d67ed
add testfor D2 and sign in assemble_op
Ylva Rydin <ylva.rydin@telia.com>
parents:
826
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36 |
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Ylva Rydin <ylva.rydin@telia.com>
parents:
826
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37 [D2,e_l,e_r,d1_l,d1_r] = assemble_D2('D2_standard_2',h,m); |
d1e5143d67ed
add testfor D2 and sign in assemble_op
Ylva Rydin <ylva.rydin@telia.com>
parents:
826
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38 |
d1e5143d67ed
add testfor D2 and sign in assemble_op
Ylva Rydin <ylva.rydin@telia.com>
parents:
826
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39 verifyEqual(testCase,D2,op.D2,'AbsTol',1e-10) |
d1e5143d67ed
add testfor D2 and sign in assemble_op
Ylva Rydin <ylva.rydin@telia.com>
parents:
826
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40 verifyEqual(testCase,e_l,op.e_l,'AbsTol',1e-10) |
d1e5143d67ed
add testfor D2 and sign in assemble_op
Ylva Rydin <ylva.rydin@telia.com>
parents:
826
diff
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41 verifyEqual(testCase,e_r,op.e_r,'AbsTol',1e-10) |
d1e5143d67ed
add testfor D2 and sign in assemble_op
Ylva Rydin <ylva.rydin@telia.com>
parents:
826
diff
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42 verifyEqual(testCase,d1_l,op.d1_l,'AbsTol',1e-10) |
d1e5143d67ed
add testfor D2 and sign in assemble_op
Ylva Rydin <ylva.rydin@telia.com>
parents:
826
diff
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43 verifyEqual(testCase,d1_r,op.d1_r,'AbsTol',1e-10) |
d1e5143d67ed
add testfor D2 and sign in assemble_op
Ylva Rydin <ylva.rydin@telia.com>
parents:
826
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44 end |