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annotate operator_def/assemble_D1.m @ 829:e0913772dc1c feature/operator_files

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Add D2 files
author Ylva Rydin <ylva.rydin@telia.com>
date Mon, 10 Sep 2018 19:25:41 +0200
parents f82da6644f42
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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821
95c26000c0ba Add files for parsing operator data stencil file
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
1 function [D1,e_l,e_r] = assemble_D1(stencil,h,m)
826
b94bb6ffa38b rename d2_2 to D1_standard_2
Ylva Rydin <ylva.rydin@telia.com>
parents: 824
diff changeset
2 stencil_variables = read_stencil(stencil);
828
f82da6644f42 Fixed bug in tests
Ylva Rydin <ylva.rydin@telia.com>
parents: 826
diff changeset
3 D1 = assemble_op(stencil_variables.inner_stencil,stencil_variables.boundary_stencils,m,-1)/h;
824
ed8d34894589 fix bug in assemble_D1
Ylva Rydin <ylva.rydin@telia.com>
parents: 823
diff changeset
4 [e_l, e_r] = assemble_boundary_op(stencil_variables.e,m);
821
95c26000c0ba Add files for parsing operator data stencil file
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
5 end