changeset 827:d1e5143d67ed feature/operator_files

add testfor D2 and sign in assemble_op
author Ylva Rydin <ylva.rydin@telia.com>
date Mon, 10 Sep 2018 18:50:29 +0200
parents b94bb6ffa38b
children f82da6644f42
files operator_def/assemble_op.m operator_def/assemble_opTest.m
diffstat 2 files changed, 18 insertions(+), 5 deletions(-) [+]
line wrap: on
line diff
diff -r b94bb6ffa38b -r d1e5143d67ed operator_def/assemble_op.m
--- a/operator_def/assemble_op.m	Mon Sep 10 17:48:48 2018 +0200
+++ b/operator_def/assemble_op.m	Mon Sep 10 18:50:29 2018 +0200
@@ -1,14 +1,12 @@
-function [D] = assemble_op(inner_stencil,boundary_block,m)
-  
+function [D] = assemble_op(inner_stencil,boundary_block,m,sign)  
   [height_b, width_b] = size(boundary_block);
   width_i = length(inner_stencil);
   
   max_offset = floor(width_i/2);
   diags = -max_offset:max_offset;
-  
-  
+   
   D = stripeMatrix(inner_stencil, diags, m);
   
   D(1:height_b,1:width_b) = boundary_block;
-  D(m-height_b+1:m,m-width_b+1:m) = rot90( -boundary_block ,2);
+  D(m-height_b+1:m,m-width_b+1:m) = rot90( sign*boundary_block ,2);
 end
\ No newline at end of file
diff -r b94bb6ffa38b -r d1e5143d67ed operator_def/assemble_opTest.m
--- a/operator_def/assemble_opTest.m	Mon Sep 10 17:48:48 2018 +0200
+++ b/operator_def/assemble_opTest.m	Mon Sep 10 18:50:29 2018 +0200
@@ -27,3 +27,18 @@
 verifyEqual(testCase,e_l,op.e_l,'AbsTol',1e-10)
 verifyEqual(testCase,e_r,op.e_r,'AbsTol',1e-10)
 end
+
+
+function TestAssembleD2(testCase)
+m = 10;
+op = sbp.D2Standard(m,{0 3},2);
+h = op.h;
+
+[D2,e_l,e_r,d1_l,d1_r] = assemble_D2('D2_standard_2',h,m);
+
+verifyEqual(testCase,D2,op.D2,'AbsTol',1e-10)
+verifyEqual(testCase,e_l,op.e_l,'AbsTol',1e-10)
+verifyEqual(testCase,e_r,op.e_r,'AbsTol',1e-10)
+verifyEqual(testCase,d1_l,op.d1_l,'AbsTol',1e-10)
+verifyEqual(testCase,d1_r,op.d1_r,'AbsTol',1e-10)
+end