changeset 830:e15a667ffde2 feature/operator_files

Add quadrature stencils and operator assembly. Add tests
author Vidar Stiernström <vidar.stiernstrom@it.uu.se>
date Mon, 10 Sep 2018 19:27:27 +0200
parents e0913772dc1c
children
files operator_def/H_2 operator_def/assemble_H.m operator_def/assemble_op.m operator_def/assemble_opTest.m
diffstat 4 files changed, 23 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
diff -r e0913772dc1c -r e15a667ffde2 operator_def/H_2
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/operator_def/H_2	Mon Sep 10 19:27:27 2018 +0200
@@ -0,0 +1,7 @@
+# H order 2
+
+closure
+1/2
+
+inner_stencil
+1
\ No newline at end of file
diff -r e0913772dc1c -r e15a667ffde2 operator_def/assemble_H.m
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/operator_def/assemble_H.m	Mon Sep 10 19:27:27 2018 +0200
@@ -0,0 +1,6 @@
+function [H, Hinv] = assemble_H(quadrature, h, m)
+    quadrature_variables = read_stencil(quadrature);
+    %TBD: Do we want to reuse assempbe_op here?
+    H = assemble_op(quadrature_variables.inner_stencil, quadrature_variables.closure, m, 1)*h;
+    Hinv = inv(H);
+end
\ No newline at end of file
diff -r e0913772dc1c -r e15a667ffde2 operator_def/assemble_op.m
--- a/operator_def/assemble_op.m	Mon Sep 10 19:25:41 2018 +0200
+++ b/operator_def/assemble_op.m	Mon Sep 10 19:27:27 2018 +0200
@@ -9,4 +9,4 @@
   
   D(1:height_b,1:width_b) = boundary_block;
   D(m-height_b+1:m,m-width_b+1:m) = rot90( sign*boundary_block ,2);
-end
\ No newline at end of file
+end
diff -r e0913772dc1c -r e15a667ffde2 operator_def/assemble_opTest.m
--- a/operator_def/assemble_opTest.m	Mon Sep 10 19:25:41 2018 +0200
+++ b/operator_def/assemble_opTest.m	Mon Sep 10 19:27:27 2018 +0200
@@ -42,3 +42,12 @@
 verifyEqual(testCase,d1_l,op.d1_l,'AbsTol',1e-10)
 verifyEqual(testCase,d1_r,op.d1_r,'AbsTol',1e-10)
 end
+
+function TestAssembleH(testCase)
+    m = 10;
+    op = sbp.D2Standard(m,{0 3},2);
+    h = op.h;
+    [H, Hinv] = assemble_H('H_2',h,m);
+    verifyEqual(testCase,H,op.H,'AbsTol',1e-10)
+    verifyEqual(testCase,Hinv,op.HI,'AbsTol',1e-10)
+end