annotate operator_def/D2_standard_2 @ 829:e0913772dc1c feature/operator_files

Add D2 files
author Ylva Rydin <ylva.rydin@telia.com>
date Mon, 10 Sep 2018 19:25:41 +0200
parents
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
829
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
1 # D2 order 2
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
2
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
3 boundary_stencils
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
4 1 -2 1
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
5
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
6 inner_stencil
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
7 1 -2 1
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
8
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
9 e
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
10 1 0
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
11
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
12 d1
e0913772dc1c Add D2 files
Ylva Rydin <ylva.rydin@telia.com>
parents:
diff changeset
13 -3/2 2 -1/2