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view operator_def/D1_standard_2 @ 827:d1e5143d67ed feature/operator_files

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add testfor D2 and sign in assemble_op
author Ylva Rydin <ylva.rydin@telia.com>
date Mon, 10 Sep 2018 18:50:29 +0200
parents b94bb6ffa38b
children
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# D1 order 2

boundary_stencils
-1 1 

inner_stencil
-1/2 0 1/2 

e
1 0